1. Technical Field
The present disclosure relates in general to the field of electronics, and in particular to timing clocks in electronic circuits. Still more particularly, the present disclosure relates to a clock splitter having an integrated clock frequency-divider.
2. Description of the Related Art
Timing of clock signals in an electronic circuit, including an Integrated Circuit (IC), is essential to proper operations of the circuit. Timing problems arise, however, when components of the IC are physically spaced far apart. In such scenarios, a clock signal from one component will be time-delayed before it reaches another component. If the two components have a synchronous relationship, then problems will ensue.
For example, consider the circuit shown in FIG. 1. An oscillator 100 generates a 1.0 GHz clock signal. While this clock signal frequency is useful in many components of a circuit, other components may need a lower frequency clock signal. To obtain a lower frequency, a clock frequency-divider 102 is utilized. In the example shown, clock frequency-divider 102 suppresses every other clock waveform, thus created a clock signal that has a frequency of 0.5 GHz (500 MHz).
The two (different frequency) clock signals are then sent to clock splitters 104a-b, which output two clock signals (ZC and ZB), which have the same frequency as the respective input clock signal, but are time shifted. This allows the slave latch B and the master latch C in the Shift Register Latch (SRL) 106a-e to launch and capture data stored in these elements. For example, the clock signal ZB from clock splitter 104a causes data in latch B from SRL 106a to be launched to latch C in SRL 106b. Clock signal ZC from clock splitter 104a causes latch C in SRL 106b to capture the data that was just launched from latch B in SRL 106a. Similarly, clock signals ZC and ZB from clock splitter 104a cause data to be launched and captured from latch 106b to latch 106c. 
Similarly, the clock signals ZC and ZB in clock splitter 104b cause data to be launched and captured from latch B in SRL 106d to latch C in SRL 106e. Assume that data captured in latches 106c and 106e are synchronously dependent. That is, assume that data must be captured (or launched) from these two latches at exactly the same time. Alternatively, latches 106c and 106e may be directly or indirectly coupled. If so, then the timing between these two latches must be perfectly synchronized. However, because of the distance (and distance differences) between oscillator 100 and latches 106c and 106e, such signal synchronization is difficult, if not impossible, to achieve.